Page 1 of 37 • 1822 total threads
Discussion Threads in comp.cad.cadence
1822 threads • Page 1 of 37| Thread Subject | Last Message |
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IC 5.0 Linux slow graphic
By: haneu@illegal.de on Tue, 05 Aug 2003 06:01 |
5
21 Years 11 Months ago
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Diff Pair routing in 14.2
By: "Steve" on Sun, 10 Aug 2003 14:17 |
1
21 Years 11 Months ago
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Allegro 14.2 Board Wizard Bug
By: rickyhardy@houst on Sat, 09 Aug 2003 13:04 |
2
21 Years 11 Months ago
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cad client / server..
By: ypjofficial@indi on Sat, 09 Aug 2003 13:47 |
1
21 Years 11 Months ago
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Ambit/PKS - Avoid synthesis of specific cells
By: Henning.Bahr@ncl on Wed, 30 Jul 2003 04:50 |
5
21 Years 11 Months ago
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bind keys not enabled
By: hariharan_ind@ho on Thu, 07 Aug 2003 16:45 |
2
21 Years 11 Months ago
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extract and LVS my own device
By: Matthew E Rosent on Tue, 05 Aug 2003 19:47 |
5
21 Years 11 Months ago
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Composer grid dots
By: mjruss@magnaspee on Thu, 07 Aug 2003 09:59 |
2
21 Years 11 Months ago
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siminfo error while creating netlist
By: Karthik Sundarar on Mon, 04 Aug 2003 13:23 |
6
21 Years 11 Months ago
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redisplay form on invalid input?
By: erikwanta@starba on Fri, 25 Jul 2003 16:07 |
9
21 Years 11 Months ago
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geomSize
By: mjruss@magnaspee on Fri, 01 Aug 2003 13:29 |
7
21 Years 11 Months ago
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Help regarding Virtuoso Layout editor....
By: vidhyaa123@hotma on Wed, 06 Aug 2003 15:11 |
2
21 Years 11 Months ago
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bandwidth()
By: "S. Badel" on Wed, 06 Aug 2003 13:02 |
2
21 Years 11 Months ago
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THE Verification Reference available: Bergeron's "Writing Testbenches," $46 (53% off Amazon's Price)
By: hdl_book_seller@ on Wed, 06 Aug 2003 18:20 |
1
21 Years 11 Months ago
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SJF, TJF licenses
By: dionisij@msn.com on Sat, 02 Aug 2003 20:29 |
3
21 Years 11 Months ago
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modifying_drc
By: selvakumar_in@ho on Mon, 04 Aug 2003 20:37 |
2
21 Years 11 Months ago
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SKILL Progress Bar
By: erikwanta@starba on Sun, 03 Aug 2003 17:32 |
3
21 Years 11 Months ago
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Spectre simulation ADE vs command line
By: mcdurr@yahoo.com on Fri, 01 Aug 2003 15:32 |
4
21 Years 11 Months ago
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about first encounter
By: spias@gmx.de on Tue, 05 Aug 2003 08:30 |
1
21 Years 11 Months ago
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Simulating phase noise for PFD-CP
By: cupricwhistle@ya on Sun, 03 Aug 2003 20:37 |
2
21 Years 11 Months ago
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verilog code to netlist
By: jmspam2003@yahoo on Mon, 04 Aug 2003 06:50 |
1
21 Years 11 Months ago
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statistically variable parameters
By: Badhrinath Jagan on Tue, 08 Jul 2003 23:13 |
2
21 Years 11 Months ago
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a humble request..pls help me
By: ypjofficial@indi on Sun, 03 Aug 2003 07:05 |
1
21 Years 11 Months ago
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how to recover the simulation result before the crash
By: "Ling Zhang" on Sat, 02 Aug 2003 20:44 |
1
21 Years 11 Months ago
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write_techfile ?
By: selvakumar_in@ho on Mon, 28 Jul 2003 02:56 |
3
21 Years 12 Months ago
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ipc functions and Environment Vairables
By: erikwanta@starba on Fri, 01 Aug 2003 09:15 |
1
21 Years 12 Months ago
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Flashing colors when using XFree86 with IC5.0
By: svenn.are@bjerke on Wed, 09 Jul 2003 02:21 |
10
21 Years 12 Months ago
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ISQED04, CALL FOR PAPERS
By: "INFO" on Fri, 01 Aug 2003 00:53 |
1
21 Years 12 Months ago
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license feature number mapping?
By: erikwanta@starba on Thu, 31 Jul 2003 12:58 |
2
21 Years 12 Months ago
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pls clarify my doubts
By: ypjofficial@indi on Tue, 29 Jul 2003 08:44 |
8
21 Years 12 Months ago
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lmstat reliability?
By: lynch@agere.com on Wed, 30 Jul 2003 05:25 |
2
21 Years 12 Months ago
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Computing slew rate through PSS analysis
By: cupricwhistle@ya on Mon, 28 Jul 2003 10:39 |
3
21 Years 12 Months ago
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gpdk
By: selvakumar_in@ho on Wed, 30 Jul 2003 00:07 |
3
21 Years 12 Months ago
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How to chang the clock tree structure in SE?
By: "dragon" on Mon, 28 Jul 2003 10:03 |
2
21 Years 12 Months ago
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Capacitor Layout in 0.18 um in Cadence
By: karim_abdelhalim on Thu, 24 Jul 2003 12:34 |
3
21 Years 12 Months ago
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How to draw an inductance?
By: "Boki" on Wed, 23 Jul 2003 14:11 |
2
21 Years 12 Months ago
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cadence calculator?
By: erikwanta@starba on Thu, 10 Jul 2003 20:09 |
5
21 Years 12 Months ago
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Which journal should I choose?
By: Kuan Zhou on Mon, 28 Jul 2003 11:33 |
1
21 Years 12 Months ago
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Tutorial for Cadence IC 4.4.6 set of tools
By: "rmathur" on Sat, 26 Jul 2003 01:41 |
3
22 Years ago
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How to determine capacitance of input pin with spectreS
By: Thomas Popp on Mon, 21 Jul 2003 14:13 |
9
22 Years ago
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Node capacitance?
By: "a" on Thu, 24 Jul 2003 22:01 |
2
22 Years ago
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signalscan view(modelsim) - content of memory array
By: pradeepg@vlsi1.s on Fri, 25 Jul 2003 03:56 |
1
22 Years ago
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Wha'ts the major different between HSPICE 2001.4 and HSPICE 2002.2 ?
By: "Boki" on Thu, 24 Jul 2003 16:51 |
1
22 Years ago
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A NEW MACHINE INVENTED
By: "ron kliewer" on Tue, 22 Jul 2003 17:36 |
1
22 Years ago
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clockroute in sedsm
By: "Parikshit Kumar on Mon, 21 Jul 2003 13:10 |
1
22 Years ago
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problem simulating with standard cells
By: "S. Badel" on Wed, 16 Jul 2003 10:26 |
2
22 Years ago
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Making a particular layer of a cellview(layout) invisible in top level
By: suresh j on Thu, 17 Jul 2003 12:31 |
3
22 Years ago
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layout_area
By: selvakumar_in@ho on Thu, 17 Jul 2003 20:27 |
2
22 Years ago
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hierarchical POWER_GROUP
By: "willbi" on Thu, 17 Jul 2003 17:47 |
1
22 Years ago
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How translate sdt iii files to orcad 9.2
By: m.d.meijer@hccne on Thu, 17 Jul 2003 16:05 |
1
22 Years ago
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Page 1 of 37 • 1822 total threads
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