Thread View: comp.cad.cadence
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2 total messages
Started by selvakumar_in@ho
Thu, 17 Jul 2003 20:27
layout_area
Author: selvakumar_in@ho
Date: Thu, 17 Jul 2003 20:27
Date: Thu, 17 Jul 2003 20:27
9 lines
188 bytes
188 bytes
hello , while I am drawing an inverter layout, I think about what will be the area of the chip.But I didn't know how to calculate the chip area, so kindly help me ? regards selvakumar.
Re: layout_area
Author: m_rajeswaran@yah
Date: Fri, 18 Jul 2003 07:10
Date: Fri, 18 Jul 2003 07:10
12 lines
384 bytes
384 bytes
I dont understand the reason why the chip area affects the inverter design. selvakumar_in@hotmail.com wrote in message news:<63f7196c.0307171927.5699ac09@posting.google.com>... > hello , > > while I am drawing an inverter layout, I think about what will be the > area of the chip.But I didn't know how to calculate the chip area, so > kindly help me ? > > regards > > selvakumar.
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