🚀 go-pugleaf

Matt:
As Stephane mentioned, you can use macro cell extraction in Diva to
check for top level routing connectivity.  If you are using Assura,
look into the ?blackBoxCell option in the LVS options (Assura
blackbox=Diva macrocell).
---
Erik

"S. Badel" <stephane.badel@epfl.ch> wrote in message news:<3f30b462$1@epflnews.epfl.ch>...
> i guess you should not write your own extract rules.
> what you can do is do a macro-mode extraction. this will extract
> any childs cells in your layout as "macro-cells".
> or you can tell the netlister to netlist your cell as a whole
> by creating an auLvs view for your cell.
> really, this is all a netlisting problem. check the netlist, find out
> what's wrong and then you will find how to tell the netlister
> to do what you want.
>
> i had this problem once and the easiest way i found was to make a
> copy of the layout. then i did flatten the whole layout except the cells
> i did want to have in my netlist. then i did a macro-mode extraction.
>
> maybe post the netlist and we can help
>
> regards
>
> "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
> news:Pine.LNX.4.55L-032.0308051939310.13621@unix45.andrew.cmu.edu...
> > Hi,
> > I want to LVS a large layout that has several instances of an original
> > device in it.  I use a verilog-A model for the schematic and I really just
> > want to check connectivity on the layout.  I have written an extract rul
> > file that is able to find my original device but When I try to LVS i get
> > "net list match" regardless of whether or not my layout is correct.  It
> > does successfuly extract the device but it does not check that its
> > terminal are connected correctly.
> > What do i need to create  or do to make sure the connectiviity is correct.
> > I know i am creating the correct number of pins on the device because I no
> > longer get an error about an incorrect number of pins.
> >
> > Your help is much appreciated
> >
> > Matt

i guess you should not write your own extract rules.
what you can do is do a macro-mode extraction. this will extract
any childs cells in your layout as "macro-cells".
or you can tell the netlister to netlist your cell as a whole
by creating an auLvs view for your cell.
really, this is all a netlisting problem. check the netlist, find out
what's wrong and then you will find how to tell the netlister
to do what you want.

i had this problem once and the easiest way i found was to make a
copy of the layout. then i did flatten the whole layout except the cells
i did want to have in my netlist. then i did a macro-mode extraction.

maybe post the netlist and we can help

regards

"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news:Pine.LNX.4.55L-032.0308051939310.13621@unix45.andrew.cmu.edu...
> Hi,
> I want to LVS a large layout that has several instances of an original
> device in it.  I use a verilog-A model for the schematic and I really just
> want to check connectivity on the layout.  I have written an extract rul
> file that is able to find my original device but When I try to LVS i get
> "net list match" regardless of whether or not my layout is correct.  It
> does successfuly extract the device but it does not check that its
> terminal are connected correctly.
> What do i need to create  or do to make sure the connectiviity is correct.
> I know i am creating the correct number of pins on the device because I no
> longer get an error about an incorrect number of pins.
>
> Your help is much appreciated
>
> Matt

Stephane,

Don't flatten any layout for that !

There is a special feature which do this expansion for you
during the macro-mode extraction :
Add a property to each instance to be expanded :
ivCellType = graphic

If this instance is used several time across your design hierarchy
and you need it to be always expanded, then you have to add this
property inside the master cell by adding this property for the
cellview (shift-q)

The Cadence documentation is very clear about this and I recommend
you to look at it.

Regards,
================================================================
Kholdoun TORKI
http://cmp.imag.fr
================================================================

S. Badel wrote:
> 
> i had this problem once and the easiest way i found was to make a
> copy of the layout. then i did flatten the whole layout except the cells
> i did want to have in my netlist. then i did a macro-mode extraction.

ok that's very interesting.
even though i did read the documentation i didn't
see that.
thanks for the trick.

"Kholdoun TORKI" <Kholdoun.Torki@imag.fr> wrote in message
news:3F3116E2.6040904@imag.fr...
> Stephane,
>
> Don't flatten any layout for that !
>
> There is a special feature which do this expansion for you
> during the macro-mode extraction :
> Add a property to each instance to be expanded :
> ivCellType = graphic
>
> If this instance is used several time across your design hierarchy
> and you need it to be always expanded, then you have to add this
> property inside the master cell by adding this property for the
> cellview (shift-q)
>
> The Cadence documentation is very clear about this and I recommend
> you to look at it.
>
> Regards,
> ================================================================
> Kholdoun TORKI
> http://cmp.imag.fr
> ================================================================
>
> S. Badel wrote:
> >
> > i had this problem once and the easiest way i found was to make a
> > copy of the layout. then i did flatten the whole layout except the cells
> > i did want to have in my netlist. then i did a macro-mode extraction.
>