Thread View: comp.arch.fpga
2 messages
2 total messages
Started by serard@lslsun.ep
Mon, 16 Nov 1998 00:00
Xilinx 4k programming
Author: serard@lslsun.ep
Date: Mon, 16 Nov 1998 00:00
Date: Mon, 16 Nov 1998 00:00
34 lines
1274 bytes
1274 bytes
Hi, I have to programme some xc40125xv from a 68360. The FPGAs are in synchronous paripheral mode. D[7..0] from the FPGAs are connected to D[31..24] from the 68k. CCLK is generated from a MAX7128, as the others control signals (/prog and /init). /init has an external pull up tied to 3v3. To programm, I do: - set /prog and /init down, - wait a few us (about 50 us), - release /init and set /prog high, - wait for /init to go high, - send a first CCLK pulse (320ns high), - put an 8 bits data on the bus and send 8 CCLK pulses (data are remove before the seconde pulse, pulses are generated by a control register in the MAX7128), - look if /init has gone down (no wait), - send the next byte (last datas are already in, due to 68k timmings) - and so on (send byte and look /init) for complete data (349630 bytes) - if /init goes down during the process (error!), stop it and show how many bytes were sent - at the end, look if done pin is high (fed up) and I have a probleme: after 100-150 bytes (it allways changes), the process stop, due to a low /init. and I just don't understand why. If someone could help me, I would be very gratefull, because it's for my diploma project and I'm stuck there and I don't know how to go on. Thanks every body, Sebastien
Re: Xilinx 4k programming
Author: fliptron@netcom.
Date: Mon, 16 Nov 1998 00:00
Date: Mon, 16 Nov 1998 00:00
54 lines
2288 bytes
2288 bytes
After the leading string of eight '1' bits, is the pattern 0,0,1,0 (see page 4-49 of the 1/98 data book). then 24 length count bits, then 4 more '1's. Total of 40 bits of header. If you are clocking everything correctly, you should see the exact same stuff with a 1 clock delay on the DOUT pin (right next to the DIN pin). Check that the header is coming out and it looks correct. The out going header is EXACTLY what the chip thought it got as an incomming header, so if it is incorrect, then the chip internally has not got a valid header. The random failure position suggests a clocking problem, such as a non-clean rising and falling edge of the clock. You need to check this with a 300MHz (or faster) scope. Remember to check the falling edge, as a glitch on the falling edge can look like a rising edge. Given your problem description, this seems quite likely. Philip Freidin. In article <36504487.0@dinews.epfl.ch> serard@lslsun.epfl.ch (Sebastien Erard) writes: >Hi, > >I have to programme some xc40125xv from a 68360. The FPGAs are in >synchronous paripheral mode. D[7..0] from the FPGAs are connected >to D[31..24] from the 68k. CCLK is generated from a MAX7128, as the >others control signals (/prog and /init). /init has an external >pull up tied to 3v3. > >To programm, I do: > >- set /prog and /init down, >- wait a few us (about 50 us), >- release /init and set /prog high, >- wait for /init to go high, >- send a first CCLK pulse (320ns high), >- put an 8 bits data on the bus and send 8 CCLK pulses > (data are remove before the seconde pulse, pulses are generated by > a control register in the MAX7128), >- look if /init has gone down (no wait), >- send the next byte (last datas are already in, due to 68k timmings) >- and so on (send byte and look /init) for complete data (349630 bytes) > >- if /init goes down during the process (error!), stop it and show how > many bytes were sent > >- at the end, look if done pin is high (fed up) > > >and I have a probleme: after 100-150 bytes (it allways changes), the >process stop, due to a low /init. and I just don't understand why. >If someone could help me, I would be very gratefull, because it's >for my diploma project and I'm stuck there and I don't know how to >go on. > >Thanks every body, Sebastien
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