🚀 go-pugleaf

Hi,

I have to programme some xc40125xv from a 68360. The FPGAs are in
synchronous paripheral mode. D[7..0] from the FPGAs are connected
to D[31..24] from the 68k. CCLK is generated from a MAX7128, as the
others control signals (/prog and /init). /init has an external
pull up tied to 3v3.

To programm, I do:

- set /prog and /init down,
- wait a few us (about 50 us),
- release /init and set /prog high,
- wait for /init to go high,
- send a first CCLK pulse (320ns high),
- put an 8 bits data on the bus and send 8 CCLK pulses
  (data are remove before the seconde pulse, pulses are generated by
   a control register in the MAX7128),
- look if /init has gone down (no wait),
- send the next byte (last datas are already in, due to 68k timmings)
- and so on (send byte and look /init) for complete data (349630 bytes)

- if /init goes down during the process (error!), stop it and show how
  many bytes were sent

- at the end, look if done pin is high (fed up)


and I have a probleme: after 100-150 bytes (it allways changes), the
process stop, due to a low /init. and I just don't understand why.
If someone could help me, I would be very gratefull, because it's
for my diploma project and I'm stuck there and I don't know how to
go on.

Thanks every body, Sebastien