🚀 go-pugleaf

Hi,
I want to LVS a large layout that has several instances of an original
device in it.  I use a verilog-A model for the schematic and I really just
want to check connectivity on the layout.  I have written an extract rul
file that is able to find my original device but When I try to LVS i get
"net list match" regardless of whether or not my layout is correct.  It
does successfuly extract the device but it does not check that its
terminal are connected correctly.
What do i need to create  or do to make sure the connectiviity is correct.
I know i am creating the correct number of pins on the device because I no
longer get an error about an incorrect number of pins.

Your help is much appreciated

Matt