Help] Altera FloorPlan Editor

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1 total messages Started by iccra Fri, 13 Nov 1998 00:00

#3955

Author: iccra
Date: Fri, 13 Nov 1998 00:00

6 lines
275 bytes

i have a problem of taget size of my VHDL project.
i try to minimize a number of  Altera Device's and Delay.
but my synthesized VHDL Source is larger than Altera's compiled AHDL
source and Top gdf.

i wanna know Altera FloorPlan Editor and using method.
thank you in advance.

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