🚀 go-pugleaf

Chris Eilbeck wrote:
>
> Has anyone got a use for a synthesizable implementation of DES in VHDL?
> I've done it as a learning exercise working from John Savard's
> description and could bung it on my web site if anyone is interested.
> Naturally, no warranty etc.  I assume it is legal to post crypto code on
> a web site in the UK, AFAIK there are no export control laws here.

I for one, would be interested in seeing your code. I can't comment on
any legal issues of posting it. But I believe even in the US, DES has
been declared to be OK to export now. I guess they finally figured that
DES is small potatoes compared to the other things running around out
there.

Did I read correctly that your algorithm took a 250K gate chip for
implementation? That seems like a lot! I take it that your
implementation is fully pipelined rather than sequential like a standard
CPU.


--

Rick Collins

redsp@XYusa.net

remove the XY to email me.

Chris Eilbeck wrote in message <364A3F47.F077FE6C@yordas.demon.co.uk>...
>Has anyone got a use for a synthesizable implementation of DES in VHDL?
>I've done it as a learning exercise working from John Savard's
>description and could bung it on my web site if anyone is interested.
>Naturally, no warranty etc.  I assume it is legal to post crypto code on
>a web site in the UK, AFAIK there are no export control laws here.


I think it is at the moment but the UK government is thinking about making
it illegal. I have crypto code on my web site at:

http://www.seven77.demon.co.uk/aes.htm

     Brian Gladman

Chris Eilbeck <chris@yordas.demon.co.uk> writes:

>Has anyone got a use for a synthesizable implementation of DES in VHDL?
>I've done it as a learning exercise working from John Savard's
>description and could bung it on my web site if anyone is interested.
>Naturally, no warranty etc.  I assume it is legal to post crypto code on
>a web site in the UK, AFAIK there are no export control laws here.

The EFF's Deep Crack implementation is available both in book form ("Cracking
DES") and online, there are links from the EFF home page, http://www.eff.org.
Posting the code from the UK is perfectly OK.

>It checks out OK against the validation data in the des-linux package.
>Has anyone got some test vectors with stronger provenance?  I check
>FIPS46-2 and FIPS74 but there wasn't any test data.  Someone has
>borrowed (and I think lost) my AC2 so that is out for now.

You can get a copy of the NBS/NIST test vectors (along with C code to apply
them if that's useful) as part of cryptlib,
http://www.cs.auckland.ac.nz/~pgut001/cryptlib/ - look at lib_des.c.

Peter.

In article <910869470.13339.0.nnrp-02.c2de6a96@news.demon.co.uk>,
  "Brian Gladman" <gladman@demon.co.uk> wrote:
>
> Chris Eilbeck wrote in message <364A3F47.F077FE6C@yordas.demon.co.uk>...
> >Has anyone got a use for a synthesizable implementation of DES in VHDL?
> >I've done it as a learning exercise working from John Savard's
> >description and could bung it on my web site if anyone is interested.
> >Naturally, no warranty etc.  I assume it is legal to post crypto code on
> >a web site in the UK, AFAIK there are no export control laws here.
>
> I think it is at the moment but the UK government is thinking about making
> it illegal. I have crypto code on my web site at:
>
> http://www.seven77.demon.co.uk/aes.htm
>
>      Brian Gladman

Dr Gladman is quite correct - the current export laws do not cover the
intangible export of goods from the UK.  Tangible export is currently covered
by the primary legislation "Import, Export and Customs Powers (Defence) Act
1939".

The government has a white paper entitled STRATEGIC EXPORT CONTROLS available
at: http://www.dti.gov.uk/export.control/stratex/

This details the governments worrying proposals.


Regards,

Sam Simpson
Comms Analyst
-- See http://www.hertreg.ac.uk/ss/ for ScramDisk, a free virtual disk
encryption for Windows 95/98.  PGP Keys available at the same site.

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Rickman wrote:
>
> Did I read correctly that your algorithm took a 250K gate chip for
> implementation? That seems like a lot! I take it that your
> implementation is fully pipelined rather than sequential like a standard
> CPU.

It is fully pipelined taking 4700 logic blocks on a Xilinx 4000 FPGA
(60000 gates).  I haven't done any optimisations and it may be possible
to drop the gate count with a bit of work.  This is just a first cut as
a learning exercise to date and doesn't have any useable interfaces, 64
bit parallel I/O.  A full duplex single round implementations would
probably fit on a XC4028 for about 200 quid per chip but with an
associated drop in throughput.

Chris
--
Chris Eilbeck
mailto:chris@yordas.demon.co.uk

In article <364A3F47.F077FE6C@yordas.demon.co.uk>,
Chris Eilbeck  <chris@yordas.demon.co.uk> wrote:
>Has anyone got a use for a synthesizable implementation of DES in VHDL?

I would be interested in seeing this.

..
>Naturally, no warranty etc.  I assume it is legal to post crypto code on
>a web site in the UK, AFAIK there are no export control laws here.

The UK does have export controls.  On paper they are much the same as
the US version but in practice there are a couple of major
differences.  Firstly, the DTI, at least at the implementation (as
opposed to policy) level are rational people so getting an export
license only takes a finite amount of work (as opposed to the
apparently unbounded work factor in the USA).  Secondly, and more
important to your comment, at the moment the UK export controls do not
cover intangible exports so currently is it legal to export crypto
over the net.  Furthermore, if you put your design in the public
domain another set of laws kick in and it is not export controlled at
all as far as I understand it.

You should be aware, if you do put the VHDL on your web site but do
not make it truly public domain, that the DTI have some rather poorly
drafted proposals outstanding which, among other effects, will remove
the loophole for intangible exports.  They will also violate basic
human rights with respect to free speech and completely destroy the
ability of British academics to cooperate in international research,
but that's another story.

	Nicko

--
--
Nicko van Someren        Fax: (+44)(1223)723601       Vox: (+44)(1223)723600
Mailto:nicko@ncipher.com                             http://www.ncipher.com/

> Did I read correctly that your algorithm took a 250K gate chip for
> implementation? That seems like a lot! I take it that your
> implementation is fully pipelined rather than sequential like a standard
> CPU.

We sell a sequential version.Straight unconstrained synthesis from ASIC VHDL
resulted in 239 CLBs
on a  xcs30 -4 and a speed of  about 72 Mbits/sec.
I got 124 Mbits/sec on some Altera part (again no constraints, a straight
synthesis from VHDL).
The same code in 0.5 u will run at 400Mbits/s and about 3.5 Kgates.

This assumes both encryption and decryption functionality. Encryption only
it's probably smaller and possibly faster.

> Rick Collins
>
> redsp@XYusa.net

My real email address it's in my web page (see below).

Enzo

-------------------------------------------------------------------------------

Vincenzo Liguori
Ocean Logic Pty Ltd
PO BOX 768
Manly NSW 1655
Australia

Ph : +61-2-99054152
Fax : +61-2-99050921
WWW : http://www.bigfoot.com/~oceanlogic

We studied and optimized DES for the Xilinx XC4000 series
with -3 speed grade. Here are our main results:


#pipeline stages  Mb/sec  CLBs used  device

1                 99      262        4008
2                 184     433        4013
4                 403     741        4028


We also compared loop unrolling vs. pipelingin and several
other issues. More info is in our SAC '98 paper and in Jens
Kaps' thesis, both of which can be found on our web page at

   http://ece.wpi.edu/Research/crypt

Regards,

Christof

--
***********************************************************************
                 Christof Paar,  Assistant Professor
          Cryptography and Information Security (CRIS) Group
      ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon: (508) 831 5061    email: christof@ece.wpi.edu
fax: (508) 831 5491    www:   http://ee.wpi.edu/People/faculty/cxp.html
***********************************************************************

We studied and optimized DES for the Xilinx XC4000 series
with -3 speed grade. Here are our main results:

#pipeline stages  Mb/sec  CLBs used  device

1                 99      262        4008
2                 184     433        4013
4                 403     741        4028


More info is in our SAC '98 paper and in Jens Kaps' thesis,
both of which can be found on our web page at

http://ece.wpi.edu/Research/crypt

Regards,

Christof


***********************************************************************
                 Christof Paar,  Assistant Professor
          Cryptography and Information Security (CRIS) Group
      ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon: (508) 831 5061    email: christof@ece.wpi.edu
fax: (508) 831 5491    www:   http://ee.wpi.edu/People/faculty/cxp.html
***********************************************************************

Christof Paar (christof@ece.WPI.EDU) wrote:
: We studied and optimized DES for the Xilinx XC4000 series
: with -3 speed grade. Here are our main results:

: #pipeline stages  Mb/sec  CLBs used  device

: 1                 99      262        4008
: 2                 184     433        4013
: 4                 403     741        4028

To clarify, this is 403 M *bits*/sec, about 50 Mbytes/sec.  Very nice.

: More info is in our SAC '98 paper and in Jens Kaps' thesis,
: both of which can be found on our web page at

: http://ece.wpi.edu/Research/crypt

There are plenty of other interesting crypto papers there too; worth a
look.

Andrew.