🚀 go-pugleaf

Hi,
> Has anybody found any affordable(?) JTAG interconnect testing software?
no we looked for something that way, too and did not find anything.

> We are a small company producing equipment in low volume for medical
> research. It seems that nobody has a marketing strategy that covers us
> (low budget!). I figured there must be lots of other companies in a
> similar position wanting to use JTAG but can't afford to?
We are a university's institute and are in a similar situation.
However, we use BSCAN mor for debugging than small-series production
test.
What we did was writing our own JTAG software interface.
Is is more a quick-and-dirty solution specific to our board (one ALTERA
CPLD),
but if you are interested, I could send you the program (GFORTH).

Andreas

--
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160

                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------

Edward Wallington wrote:
>
> Hi,
>
> apologies if this is slightly off subject, but I figured we must all
> have to do something about testing:

> Has anybody found any affordable(?) JTAG interconnect testing > software?

Interesting idea.  I sympathise strongly - about 12 months ago I did a
board with a 208pin QFP CPU and two FPGAs all of which had JTAG,
so I brought the TAP out to a connector but nobody ever got off their
backside to do anything about test software.  I think there is
probably a neat market niche here, but I'd be surprised if anyone
could ever make money out of it.

As I see it, small-volume system builders would find JTAG very useful
and can see how easy it is: no fundamental reason why you shouldn't
work it slowly off a PC parallel port, and for our sort of quantities
a reliable but slow JTAG test taking 10 minutes or more would be
time well spent.  But there are many obstacles:
1)
low level driver software to shift bits through the TAP - this is
dead easy
2)
Interface from CAD PCB layout tools' netlists, so we can decide
what tests to perform
3)
Boundary-scan-description-language (BSDL) parser so that we can
decide what bit patterns to shift in and out in order to test
various nets
4)
Getting BSDL files out of your device suppliers in machine-readable
form rather than scribbled on the back of a cigarette packet
5)
Test pattern generation software, driven by (2) and (3), to create
an optimal set of tests that will exercise your PCB's netlist

The laughable proliferation of obscure, proprietary, incompatible file
formats for the various CAD data makes this surprisingly hard.  And
that's why JTAG Technologies and so forth need to charge �20k per
seat.  JTAG Technologies have some (yet again) proprietary file
formats that they use for describing memory arrays that are attached
to your JTAG-compliant parts, so that you can do memory tests too.

The EDA companies will rot in purgatory for the hassle they have
inflicted on us through their inability to settle on a simple,
uniform, TEXT-BASED data interchange format IN THE PUBLIC DOMAIN.
(Sorry, _which_ version of EDIF is it that you support?...)  But
until the final day of judgment, it's the poor punters like you and
me who suffer.

Meanwhile, has any PERL guru out there got (a) a BDSL parser,
(b) a universal netlist translator?

frustratedly

Jonathan Bromley

I don't really understand the motivation for using JTAG on an SRAM based FPGA.
With relatively little effort, you can design a test application for the FPGA
that tests the FPGA's interconnect and any memory connected to the FPGA at
system speeds.  If the intervening logic is surrounded by FPGAs you can test
that at speed with FPGA test programs too.  Reconfiguration is an extremely
powerful debug and test tool, so why not use it.  I discuss this test
philosophy and the benefits obtained in a paper I presented this fall.  That
paper, "An FPGA based processor yields a real time high fidelity radar
environment simulator" is available on my website in adobe acrobat format.

Jonathan Bromley wrote:

> Edward Wallington wrote:
> >
> > Hi,
> >
> > apologies if this is slightly off subject, but I figured we must all
> > have to do something about testing:
>
> > Has anybody found any affordable(?) JTAG interconnect testing > software?
>
> Interesting idea.  I sympathise strongly - about 12 months ago I did a
> board with a 208pin QFP CPU and two FPGAs all of which had JTAG,
> so I brought the TAP out to a connector but nobody ever got off their
> backside to do anything about test software.  I think there is
> probably a neat market niche here, but I'd be surprised if anyone
> could ever make money out of it.
>
> As I see it, small-volume system builders would find JTAG very useful
> and can see how easy it is: no fundamental reason why you shouldn't
> work it slowly off a PC parallel port, and for our sort of quantities
> a reliable but slow JTAG test taking 10 minutes or more would be
> time well spent.  But there are many obstacles:
> 1)
> low level driver software to shift bits through the TAP - this is
> dead easy
> 2)
> Interface from CAD PCB layout tools' netlists, so we can decide
> what tests to perform
> 3)
> Boundary-scan-description-language (BSDL) parser so that we can
> decide what bit patterns to shift in and out in order to test
> various nets
> 4)
> Getting BSDL files out of your device suppliers in machine-readable
> form rather than scribbled on the back of a cigarette packet
> 5)
> Test pattern generation software, driven by (2) and (3), to create
> an optimal set of tests that will exercise your PCB's netlist
>
> The laughable proliferation of obscure, proprietary, incompatible file
> formats for the various CAD data makes this surprisingly hard.  And
> that's why JTAG Technologies and so forth need to charge �20k per
> seat.  JTAG Technologies have some (yet again) proprietary file
> formats that they use for describing memory arrays that are attached
> to your JTAG-compliant parts, so that you can do memory tests too.
>
> The EDA companies will rot in purgatory for the hassle they have
> inflicted on us through their inability to settle on a simple,
> uniform, TEXT-BASED data interchange format IN THE PUBLIC DOMAIN.
> (Sorry, _which_ version of EDIF is it that you support?...)  But
> until the final day of judgment, it's the poor punters like you and
> me who suffer.
>
> Meanwhile, has any PERL guru out there got (a) a BDSL parser,
> (b) a universal netlist translator?
>
> frustratedly
>
> Jonathan Bromley



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